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A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

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8 Author(s)
Arima, Y. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Mashiko, K. ; Okada, K. ; Yamada, T.
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A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0-μm double-poly-Si double-metal CMOS technology. The operation speed is higher than 1×1012 connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 11 )