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Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond

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5 Author(s)
Kikuda, S. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Miyamoto, H. ; Mori, S. ; Niiro, M.
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An optimized redundancy scheme for 64-Mb dynamic RAM (DRAM) and beyond that is based on a failure-related yield model is described. This model accounts for three-dimensional memory cell structures and individual design rules used in individual sections of the chip. Failure-mode parameters for the model are determined by performing a trial fuse-blowing test on 4-Mb DRAMs. The test employs a memory tester without requiring complicated visual inspections. The dependence of the yield on block division and the number of spare elements for a 64-Mb DRAM are investigated. In the estimation as a redundancy scheme for the 64-Mb DRAM, more than two spare rows and two spare columns in 1-Mb or less subblocks are shown to be necessary

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Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 11 )