Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.