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Performance analysis of low-power 1-bit CMOS full adder cells

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3 Author(s)
Shams, A.M. ; Intel Corp., Hillsboro, OR, USA ; Darwish, T.K. ; Bayoumi, M.A.

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 1 )

Date of Publication:

Feb. 2002

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