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Leakage control with efficient use of transistor stacks in single threshold CMOS

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4 Author(s)
M. C. Johnson ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; D. Somasekhar ; Lih-Yih Chiou ; K. Roy

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 1 )