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Hybrid higher radix JK flipflop sequencer with ASIC implementation potential

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4 Author(s)
J. A. C. Webb ; Dept. of ELectr. Electron. Eng., Ulster Univ., Newtonabbey, UK ; S. M. N. Forbes ; J. Wilson ; S. J. Laverty

The hybrid design of a higher radix JK edge-triggered flip-flop sequencer is presented. A ternary implementation is considered with its associated action tables. The potential for formal design of higher radix MVL sequential systems is considered and linear sequential circuit applications are indicated.

Published in:

Electronics Letters  (Volume:27 ,  Issue: 21 )