By Topic

Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ohno, K. ; NTT Radio Commun. Syst. Lab., Kanagawa-ken, Japan ; Adachi, F.

A fast clock synchroniser that quickly adjusts the initial phase of the DPLL output clock to the input signal (receiver detector output) at the beginning of acquisition is proposed for burst QDPSK signal reception. The synchroniser performance is given in terms of nondetection rate (NDR) of the unique word following the clock synchronisation preamble. Measured results clearly indicate that the proposed synchroniser achieves faster synchronisation than the conventional binary quantised DPLL clock synchroniser.

Published in:

Electronics Letters  (Volume:27 ,  Issue: 21 )