Referenced Items are not available for this document.
A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:37
,
Issue:
3
)
Date of Publication: Mar 2002
- Page(s):
- 404 - 412
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7207900
- Digital Object Identifier :
- 10.1109/4.987093
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Mar 2002
- Sponsored by :
- IEEE Solid-State Circuits Society
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