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A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

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2 Author(s)
Foley, D.J. ; Parthus Technol., Dublin, Ireland ; Flynn, M.P.

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 1013 for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm2, and dissipates 400 mW from a 3.3-V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 3 )

Date of Publication:

Mar 2002

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