A low-power current mode bipolar frequency divider is discussed. Low-power consumption is achieved owing to the design strategy being based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations
Published in:
Electronics Letters
(Volume:38
,
Issue:
4
)
Date of Publication: 14 Feb 2002