By Topic

Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Qi Wang ; Cadence Design Syst. Inc., San Jose, CA, USA ; Vrudhula, S.B.K.

Addresses the problem of delay constrained minimization of standby power of CMOS digital circuits that are implemented with dual-Vt technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. Three efficient algorithms that operate on a gate level netlist are described. Each algorithm assigns one of two threshold voltages (high and low Vt) to each transistor so that the standby power dissipation is minimized without violating a user specified delay constraint. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any increase in delay when compared to the configuration in which all devices are at the low Vt

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 3 )