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A flexible register access control for programmable protocol processors

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3 Author(s)
Y. Ma ; Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden ; A. Jantsch ; H. Tenhunen

We investigate a programmable processor architecture for internet protocol processing and use IP packet forward as a case study. We focus on flexible register access capability to support packet analysis and encapsulation. Compared to general-purpose superscalar microprocessors, our architecture achieves at least a two-fold improvement in performance

Published in:

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on  (Volume:1 )

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