A high speed CMOS current mode flash analog to digital converter is proposed. The design uses a generic cell structure that decreases circuit area for large implementations of the design. A single cell is tested for design constraints, and design constraint solutions are discussed
Published in:
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
(Volume:1
)
Date of Conference: 2001