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With increasing packaging density and Si wafer size in the ULSI process, higher qualities are required for a Si wafer, Recently, an important quality indicator of the Si wafer was derived, that is the flatness with a spatial wavelength of several nanometer size which exists on a Si surface, called nano-topography. The reason is that CMP (chemical mechanical polishing) used for STI (shallow trench isolation) in the device process generates the nano-topography on the Si wafer surface, thereby degrading the uniformity of the Si oxide thickness. The Si wafer manufacturers have made efforts to establish a removal technology for the nano-topography in the fabrication process, however, no one has been successful in providing a technology by which the nano-topography once it is generated is removed positively. We has developed the NC-LDE technology (Numerically Controlled Local Dry Etching) by fusing the local dry etching technology with numerically control technologies to meet the requirement of Si wafer flatness, and NC-LDE is now utilized in production lines. Accordingly, this paper reports on the removal performance of the present nano-topography by employing the NC-LDE technology.