By Topic

E-BIST: enhanced test-per-clock BIST architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Y. Son ; Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea ; J. Chong ; G. Russell

A new enhanced built-in self-test (E-BIST) architecture, that is suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS (Self-Test Using MISR and Parallel Shift-register sequence generators), which uses a linear feedback shift register (LFSR) as the test generator, a multiple-input shift register (MISR) as the response compactor and shift register latch (SRL) channels as multiple scan paths. In E-BIST, a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS technique. It is also shown that the masking probability of the proposed SRL channel structure is 21-(N+L), where N is the number of test patterns and L is the length of the SRL channel. The results of experiments on ISCAS 89 (International Symposium on Circuits And Systems 1989) benchmark circuits show that this architecture is also suitable for robustly detecting path delay faults, with improved fault coverage, when the Hamming distance of the data in the SRL channel is considered

Published in:

IEE Proceedings - Computers and Digital Techniques  (Volume:149 ,  Issue: 1 )