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Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

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3 Author(s)
Semenov, O. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Pradzynski, A. ; Sachdev, M.

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:15 ,  Issue: 1 )