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Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation: a summary

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2 Author(s)
Pandey, M. ; CAD Tools, Verplex Syst., Milpitas, CA, USA ; Bryant, R.E.

Summary form only given. We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits. Symmetries in circuits are classified as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling of data values, and mixed structural-data symmetries. We use graph isomorphism testing and symbolic simulation to verify the symmetries in the original circuit. Using conservative approximations, we partition a circuit to expose the symmetries in its components, and construct reduced system models which can be verified efficiently. Introducing X-drivers into switch-level circuits simplifies the task of creating conservative approximations of switch-level circuits. Our empirical results show that exploiting symmetry with conservative approximations can allow one to verify systems several orders of magnitude larger than otherwise possible. We present results of verifying Static Random Access Memory (SRAM) circuits with up to 1.5 million transistors

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Circuits and Systems Magazine, IEEE  (Volume:1 ,  Issue: 4 )