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An architecture and implementation of MPEG audio layer III decoder using dual-core DSP

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5 Author(s)
Kyu Lee ; Samsung Thales Co. Ltd., Kyungki-Do, South Korea ; Keun-Sup Lee ; Tae-Hoon Hwang ; Young-cheol Park
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A new architecture for the MP3 decoding system is proposed and implemented. The proposed system is based on a processor employing a dual-core (DSP and RISC) architecture. The MP3 decoding algorithm is implemented using the DSP core with high accuracy, and the RISC core performs bitstream buffering and system control in conjunction with a user interface. The system with this configuration can support an efficient parallel processing between DSP and RISC cores, so that it is possible to minimize the computational overhead. The implemented system employs a flash memory card for the storage, and it has a file management system that is compatible with PC. Also, it supports all sampling rates and data rates specified in MPEG-1/2 standards. The MP3 decoder developed is suitable for portable communication devices such as cellular telephones since it features high audio quality, low-power consumption and cost effectiveness

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Consumer Electronics, IEEE Transactions on  (Volume:47 ,  Issue: 4 )