Scheduled System Maintenance:
On Wednesday, July 29th, IEEE Xplore will undergo scheduled maintenance from 7:00-9:00 AM ET (11:00-13:00 UTC). During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

A 3.3-V, 2-GHz CMOS low noise amplifier

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Hui Zhao ; ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China ; Junyan Ren ; Qianling Zhang

A CMOS low noise amplifier is designed based on a narrowband LC-tuned cascode topology. With a standard 0.6 micron CMOS technology, this technique is applied to design a 3.3 V LNA operating at 2 GHz for IMT2000 band application. On-chip inductors have been used. Simulation results show that the LNA is featured with a gain of 18 dB, noise figure of 2.3 dB, IIP3 of -4.9 dBm, power dissipation of 33.9 mW, and well-matched inputs

Published in:

ASIC, 2001. Proceedings. 4th International Conference on

Date of Conference: