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Study of test approach for IP cores applicable to SOC designs

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3 Author(s)
M. W. T. Wong ; Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Kowloon, China ; K. Y. Ko ; Y. S. Lee

A test approach for testing Intellectual Property (IP) analog/mixed-signal cores is presented. The proposed procedure comprises a two-phase test design process: an equivalent fault analysis is carried out in the initial phase, followed by a built-in self-test (BIST) technique based on the weighted sum of selected node voltages. Each phase of the procedure has been validated with example circuits. Besides high fault coverage, the proposed BIST technique only needs an extra testing output pin, and only a single DC stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for the testing environment of IP cores

Published in:

ASIC, 2001. Proceedings. 4th International Conference on

Date of Conference:

2001