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Decrease power consumption using a programmable logic device

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1 Author(s)
Jenkins, J. ; Xilinx Inc, San Jose, CA, USA

This paper describes system design techniques using a low power CoolRunnerTM CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to off-load operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings

Published in:

ASIC, 2001. Proceedings. 4th International Conference on

Date of Conference:

2001

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