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An efficient VLSI architecture for 2D-DCT using direct method

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4 Author(s)
Bian Li Jian ; Microelectron. Dept., Fudan Univ., Shanghai, China ; Zeng Xuan ; Tong Jia Rong ; Liu Yue

An efficient VLSI architecture for 8×8 two-dimensional (2D) discrete cosine transform (DCT) is proposed in this paper. It is a folded architecture using direct method. It can compute 2D-DCT of a 12-b 8×8 block using one 1D-DCT unit without transpose memory. Taking advantage of the direct method, the total number of multiplications in the proposed architecture is only half of that required for row-column method. It, in turn, results in the doubled operating speed compared with those conventional implementations with row-column method. Under 0.6 μm CMOS and double metal technology, the proposed architecture presents a chip with core size 3.9×0.9 mm2, transistor count 114 K and clock rate 200 MHz

Published in:

ASIC, 2001. Proceedings. 4th International Conference on

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