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Using a hardware model checker to verify software

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3 Author(s)
Edwards, S.A. ; Dept. of Comput. Sci., Columbia Univ., New York, NY, USA ; Ma, T. ; Damiano, R.

A variety of new algorithms has begun to enable model checking of industrial-sized netlists. This work attempts to apply that technology to the verification of embedded software: C programs that manipulate integers and contain unstructured control flow, but are not recursive and do not dynamically allocate memory. We describe a synthesis procedure for translating a subset of C into a netlist and present experiments that show the models it builds seem to be harder to verify than typical hardware circuits, suggesting the problem has a different character. Although we only have preliminary experimental results, they help to identify the challenges inherent in verifying this class of software and leave open the possibility of more successful approaches

Published in:

ASIC, 2001. Proceedings. 4th International Conference on

Date of Conference:

2001

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