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A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

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8 Author(s)
Jae-Kyung Wee ; Memory R&D Div., Hynix Semicond. Inc., Kyoungki, South Korea ; Kyeong-Sik Min ; Jong-Tai Park ; Sang-Pil Lee
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A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of VCC and -VCC, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-μm triple-well 256-M SDRAM

Published in:

IEEE Journal of Solid-State Circuits  (Volume:37 ,  Issue: 2 )