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CMOS technology scaling continues to be the main driving force behind the advancement of high-performance microprocessors. As the feature size of CMOS transistors shrinks below 0.13 μm, and gate delay is rapidly reduced below 20 ps, the frequency of leading edge microprocessors has well exceeded the 1 GHz barrier now. The combination of both transistor and frequency scaling has created many new challenges in high-speed CPU design. This paper addresses many of the key technical challenges in today's multi-GHz CPU design, including low-power and low-leakage design, high-speed and skew tolerant latching strategy, on-die high-speed cache, and robust design against soft-error. Potential design solutions are discussed.