By Topic

The challenges and opportunities in GHz microprocessor design on 0.13 μm and beyond technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Zhang, K.X. ; Intel Technol. & Res. Labs, Intel Corp., Hillsboro, OR, USA

CMOS technology scaling continues to be the main driving force behind the advancement of high-performance microprocessors. As the feature size of CMOS transistors shrinks below 0.13 μm, and gate delay is rapidly reduced below 20 ps, the frequency of leading edge microprocessors has well exceeded the 1 GHz barrier now. The combination of both transistor and frequency scaling has created many new challenges in high-speed CPU design. This paper addresses many of the key technical challenges in today's multi-GHz CPU design, including low-power and low-leakage design, high-speed and skew tolerant latching strategy, on-die high-speed cache, and robust design against soft-error. Potential design solutions are discussed.

Published in:

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on  (Volume:2 )

Date of Conference:

22-25 Oct. 2001