By Topic

High-k gate dielectrics for sub-100 nm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
S. J. Lee ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; C. H. Lee ; Y. H. Kim ; H. F. Luan
more authors

In this paper, the materials and processing challenges for the fabrication of high-quality. ultra-thin (EOT<1 run) high-K gate stack for sub-100 nm CMOS technology are reviewed along with our recent results on CVD HfO2. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest EOT are discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and high-K/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in the high-K gate stack. Both poly-Si and metal nitrides are explored as possible gate electrode materials arid the upper thermal budget limit for such materials are discussed

Published in:

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on  (Volume:1 )

Date of Conference:

2001