A new compact DC model of floating gate memory cells without capacitive coupling coefficients

This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively the complete DC electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on E/sup 2/PROM and flash memory cells manufactured in existing technology (0.35 /spl mu/m and 0.25 /spl mu/m) by STMicroelectronics.