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We demonstrate a novel optical time division multiplexing packet-level system-synchronization and address-comparison technique, which relies on cascaded semiconductor-based optical logic gates operating at 50-Gb/s line rates. Synchronous global clock distribution is used to achieve fixed length packet-synchronization that is resistant to channel-induced timing delays, and straightforward to achieve using a single optical logic gate. Four-bit address processing is achieved using a pulse-position modulated header input to a single optical logic gate, which provides Boolean XOR functionality, low latency, and stability over >1 h time periods with low switching energy <100 fJ.
Date of Publication: Feb. 2002