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High-speed and reduced-area modular adder structures for RNS

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1 Author(s)
A. A. Hiasat ; Electron. Eng. Dept., Princess Sumaya Univ. for Technol., Amman, Jordan

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we introduce a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay

Published in:

IEEE Transactions on Computers  (Volume:51 ,  Issue: 1 )