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A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we introduce a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay
Published in:
Computers, IEEE Transactions on
(Volume:51
,
Issue:
1
)
Date of Publication: Jan 2002
- Page(s):
- 84 - 89
- ISSN :
- 0018-9340
- INSPEC Accession Number:
- 7157575
- Digital Object Identifier :
- 10.1109/12.980018
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Jan 2002
- Sponsored by :
- IEEE Computer Society
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