Referenced Items are not available for this document.
Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15 nm. Gate delays (CV/I) of 0.29 ps for n-channel FET and 0.68 ps for p-channel FET are achieved at a supply voltage of 0.8 V. Energy-delay products are 42 pJ-ps/m for an n-channel FET and 97 pJ-ps/m for a p-channel FET, respectively. To our knowledge; these numbers are the best reported to date.
Published in:
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Date of Conference: 2-5 Dec. 2001
- Page(s):
- 11.7.1 - 11.7.3
- Meeting Date :
- 02 Dec 2001-05 Dec 2001
- Print ISBN:
- 0-7803-7050-3
- INSPEC Accession Number:
- 7239091
- Conference Location :
- Washington, DC, USA
- Digital Object Identifier :
- 10.1109/IEDM.2001.979669
- Product Type:
- Conference Publications
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