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Enhanced performance of strained Strained-Si MOSFETs on CMP sige virtual substrate

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5 Author(s)
Sugii, N. ; Central Research Laboratory, Hitachi, Ltd. ; Hisamoto, D. ; Washio, K. ; Yokoyama, N.
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Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ~1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff = 0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001