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We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO/sub 2/) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 /spl Aring/ with a leakage current 1000/spl times/ lower than SiO/sub 2/ was obtained for a 30 /spl Aring/ HfO/sub 2//12 /spl Aring/ interfacial oxide stack. In this paper, we present results on the physical and electrical characterization.