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High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE

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28 Author(s)
Inaba, S. ; Syst. LSI R&D Center & Process & Manuf. Eng. Center, Toshiba Corp. Semicond. Co., Japan ; Okano, K. ; Matsuda, S. ; Fujiwara, M.
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35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001