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High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

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20 Author(s)
Narasimha, S. ; IBM Microelectron. Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA ; Ajmera, A. ; Park, H. ; Schepis, D.
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This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001