Overcoming Cu/CVD low-k integration challenges in a high performance interconnect technology

In this paper we describe how several challenges have been overcome in the integration of a high performance, manufacturable, Cu/CVD low-k (Coral) 0.13 /spl mu/m interconnect technology. Specifically, we discuss solving issues with 193 nm lithography for M1 using different hardmask schemes, and the challenges of 248 nm trench resist poisoning due to N-H evolution from open vias in a full via first dual damascene scheme. Optimization of the dual damascene dielectric stack and Cu CMP with regard to reliability concerns are also elucidated. Yield and reliability data are provided that demonstrate the manufacturability of the integration solutions that are discussed.