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A new multiple transistor parameter design methodology for high speed low power SoCs

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2 Author(s)
Takeuchi, K. ; Silicon Syst. Res. Labs, NEC, Kanagawa, Japan ; Mogami, T.

A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001

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