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MOSFET design of 100 nm node low standby power CMOS technology compatible with embedded trench DRAM and analog devices

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24 Author(s)
Oishi, A. ; Syst. LSI Div., Toshiba Corp., Kanagawa, Japan ; Hasumi, R. ; Okayama, Y. ; Miyashita, K.
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Demonstrates an optimum design of low leakage 85nm gate CMOSFET (I/sub off//spl les/3pA//spl mu/m) for 100nm technology node. Gate dielectric module has been optimized to achieve low gate leakage, low flicker noise and sufficiently high driving current. Deep source/drain design is strongly restricted from controlling junction leakage current when integration of trench DRAM cell is considered. Especially, for nMOSFET, deep junction is formed only by using phosphorus to suppress defect creation. Short channel immunity and suppression of gate depletion are achieved simultaneously by introducing gate pre-doping technique. In addition, channel and halo profiles are optimized to reduce band-to-band tunneling (BTBT) current. As a result, we have achieved excellent performance of /spl Sigma/CV/I(=CV/I/sub dn/+CV/I/sub dp/)=10.8psec with I/sub off/=3pA//spl mu/m at V/sub dd/ of 1.2V.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001