Cart (Loading....) | Create Account
Close category search window
 

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

24 Author(s)
Kedzierski, J. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Fried, D.M. ; Nowak, E.J. ; Kanarsky, T.
more authors

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.