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In this paper, we intensively investigated the influence of thermally induced stress by rapid thermal annealing (RTA) on DRAM data retention time. Methods of reducing thermal stress induced by RTA and the optimum location of RTA (to suppress tDPL fail) were proposed through our extensive experimental results. Low temperature (below 800/spl deg/C) BPSG flow annealing following RTA after capacitor formation eliminated the residual stress, and resulted in dramatically improved data retention time characteristics by 120%. By adoption of thin buffer oxide (/spl sim/100 /spl Aring/) under gate spacer SiN film, we solved the problem of hot carrier degradation of cell transistor by reduced trap sites by virtue of the stress-buffering role, and additionally improved data retention time by 60%.