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A 1.29 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.12 um spacer-on-stopper (SOS) CMOS technology

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15 Author(s)
Sung-Bong Kim ; TD Team, Samsung Electron. Co. Ltd., Gyungki-Do, South Korea ; Do-Hyung Kim ; Kwang-Ok Koh ; Yong Park
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We have developed a 1.29 um2 full CMOS SRAM cell for low power applications, which is the world-smallest one by using 0.12 um single gate CMOS technology and optical enhancement techniques for extending use of 248 nm KrF lithography. It includes (1) 0.28 um pitch contacts formed by aerial image controlled patterns on phase shift mask (PSM) and photo resist flow, (2) gate patterns with 0.24 um pitch, (3) 0.13 um buried channel pMOS, and (4) spacer-on-stopper (SOS) MOSFET structure for expanding contact area and reducing band-to-band tunneling leakage.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001