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A high density 0.10 /spl mu/m CMOS technology using low K dielectric and copper interconnect

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51 Author(s)
Parihar, S. ; Motorola Digital DNA Labs. & AMD Technol. Dev. Group, Austin, TX, USA ; Angyal, M. ; Boeck, B. ; Reber, D.
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In this work components of the next generation 0.10 /spl mu/m CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 /spl Aring/ gate oxide (24 /spl Aring/ inversion Tox) while low power devices use 25 /spl Aring/ gate oxide (31 /spl Aring/ inversion Tox) for reduced gate leakage. Gate lengths range from 65 nm for the high performance devices to 90 nm for the low power devices. Both 3.3 V and 2.5 V I/Os are supported using 70 /spl Aring/ and 50 /spl Aring/ oxide devices. The backend employs low-k (k/spl sim/3) dielectric with multiple levels of Cu metallization. The high density 6T SRAM cell size is 1.33 /spl mu/m/sup 2/.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001