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Design and analysis of even-sized binary shuffle-exchange networks for multiprocessors

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1 Author(s)
Padmanabhan, K. ; AT&T Bell Lab., Murray Hill, NJ, USA

The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer ⩾log2N or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural and dynamic properties of the network are established, contrasting the behavior of the power-of-two and composite sized systems. The performance of the network in a stochastic environment is investigated analytically. It is shown that the shuffle-exchange networks behave in much the same way with respect to traffic and buffer capacity regardless of whether the system size is a power of two or not

Published in:

Parallel and Distributed Systems, IEEE Transactions on  (Volume:2 ,  Issue: 4 )

Date of Publication:

Oct 1991

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