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Power model for DCFL family

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6 Author(s)
Garcia, J. ; Appl. Microelectron. Res. Inst., Univ. of Las Palmas de Gran Canaria, Spain ; Hernandez, A. ; del Pino, J. ; Sendra, J.R.
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A model to estimate power consumption in GaAs direct coupled FET logic (DCFL) family, which is based on sensitivity computations, is reported. Comparisons against SPICE simulations show errors smaller than 5% in power consumption estimation, while CPU time is reduced by more than two orders of magnitude

Published in:

Electronics Letters  (Volume:38 ,  Issue: 1 )

Date of Publication:

3 Jan 2002

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