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A new test algorithm for bit-line sensitive faults in super high density memories

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3 Author(s)
Dong-Chual Kang ; Sch. of Electrical, Electron. & Autom. Eng., Ulsan Univ., South Korea ; Jong-Hwa Lee ; Sang-Bock Cho

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. Conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. A new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is a minimum size for NBLSF detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure (i.e., write→refresh→read). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults

Published in:

Science and Technology, 2001. KORUS '01. Proceedings. The Fifth Russian-Korean International Symposium on  (Volume:1 )

Date of Conference:

26 Jun-3 Jul 2001

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