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We present a novel technique for estimating individual wire lengths in a given standard-cell-based design during the technology mapping phase of logic synthesis. The proposed method is based on creating a black box model of the place and route tool as a function of a number of parameters, which are all available before layout. The place and route tool is characterized, only once, by applying it to a set of typical designs in a certain technology. We also propose a net bounding box estimation technique based on the layout style and net neighborhood analysis. We show that there is inherent variability in wire lengths obtained using commercially available place and route tools-wire length estimation error cannot be any smaller than a lower limit due to this variability. The proposed model works well within these variability limitations.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:9 , Issue: 6 )
Date of Publication: Dec. 2001