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A technique for correction of parasitic capacitance on microwave ft measurements of MESFET and HEMT devices

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3 Author(s)
M. Feng ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; C. L. Lau ; C. Ito

A technique for determining the parasitic capacitance attributed to device layout geometry is described. This simple technique requires only on-wafer, cascade probe measurements on devices with varying gate widths. This technique will assist in the optimization of device layout design and in improving modeling performance for microwave and millimeter-wave applications

Published in:

IEEE Transactions on Microwave Theory and Techniques  (Volume:39 ,  Issue: 11 )