By Topic

Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Hsin-Chin Jiang ; Chyh-Yih Chang

A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad

Published in:

IEEE Transactions on Electron Devices  (Volume:48 ,  Issue: 12 )