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Pseudo-SOI: p-n-p channel-doped bulk MOSFET for low-voltage high-speed applications

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3 Author(s)
Miyamoto, M. ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; Nagai, R. ; Nagano, T.

A pseudo-silicon-on-insulator (P-SOI) MOSFET fabricated using a bulk substrate has been developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFET, without problems caused by the usage of an SOI substrate. It features a p-n-p channel profile, in which a sandwiched thin n-type layer is fully depleted by the internal built-in potential. The thin n-type layer expands the depletion layer in the inversion state and reduces the vertical electric field at the MOS interface. As a result, the P-SOI MOSFET has a high drain-current drivability, a small subthreshold swing, and a low substrate-bias coefficient. A TiN gate electrode, which has a near midgap work function, is used to achieve optimum threshold voltage. It also increases the drain current by reducing the gate-electrode depletion. Counter doping to the buried p-type layer below the source and drain reduces junction capacitances. The subthreshold swing of the fabricated 0.25-μm-gate-length P-SOI MOSFET becomes 73 mV/decade. Its drain current is 25% higher, substrate-bias coefficient is 40% lower, and source/drain junction capacitance is 60% lower, than those of a control MOSFET

Published in:

Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 12 )

Date of Publication:

Dec 2001

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