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A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

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4 Author(s)
Noda, K. ; ULSI Device Dev. Div, NEC Corp., Kanagawa, Japan ; Matsui, K. ; Takeda, K. ; Nakamura, N.

This paper presents a loadless CMOS four-transistor (4T) cell for very high density embedded SRAM applications. Using 0.18-μm CMOS technology, the memory cell size is 1.9344 μm2 (1.04 μm×1.86 μm), which is 35% smaller than a six-transistor (6T) cell using the same design rule. The newly developed CMOS 4T-SRAM cell operates with high stability at 1.8 V, even though its designed cell ratio is 1.0 to minimize the area. A pair of pMOS transfer transistors is used to store and retain full-swing signals in the cell without a refresh cycle. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load

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Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 12 )